vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com vc-709 hcsl, lvds, lvpecl crystal oscillator data sheet vectrons vc-709 crystal oscillator is a quartz stabilized, di erential output oscillator, operating o a 2.5 or 3.3 volt supply in a hermetically sealed 5x7 ceramic package. ultra low jitter performance, 3rd ot or fundamental crystal design ? 13.500-170.0000mhz output frequencies ? low power ? 400ps max rise and fall time ? excellent power supply rejection ratio ? enable/disable ? 3.3 or 2.5v operation ? -10/70c or -40/85c operation ? hermetically sealed 5x7 ceramic package ? product is compliant to rohs directive ? and fully compatible with lead free assembly features applications description vc-709 block diagram phase noise pci express ? ethernet, gbe, synchronous ethernet ? fiber channel ? enterprise servers ? telecom ? clock source for a/ds, d/as ? driving fpgas ? test and measurement ? pon ? medical ? cots ? v dd output e/d or nc gnd oscillator crystal e/d or nc complementary output voltage regulator page1
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com page2 performance speci cations table 1. electrical performance, lvpecl option parameter symbol min typical maximum units supply voltage 1 v dd 3.135 2.375 3.3 2.5 3.465 2.625 v v current (no load) i dd 35 50 ma frequency nominal frequency f n 13.5 170.000 mhz stability ,3 (ordering option) 25, 50 or 100 ppm outputs output logic levels 4 output logic high output logic low v oh v ol v dd -1.085 v dd -1.830 v dd -0.880 v dd -1.555 v v output rise and fall time 3 t r /t f 500 ps load 50 ohms into v dd -1.3v duty cycle 4 45 55 % jitter, 156.250mhz 5 12khz-50mhz 12khz -20mhz 10khz-1mhz j 200 150 100 fs fs fs period jitter 6 rms p/p cycle-cycle 6 rms p/p random jitter 7 deterministic jitter 7 j 1.1 10.5 1.9 17.7 2.2 0 ps ps ps ps ps ps enable/disable output enabled 8 output disabled v ih v il 0.7*v dd 0.3*v dd v v disable time t d 200 ns enable/disable leakage current 200 ua start-up time t su 2ms operating temp. (ordering option) t op -10/70 or -40/85 c package size 5.0 x 7.0 x 1.6 mm 1. the vc-709 power supply pin should be ltered, eg, a 0.1 and 0.01uf capacitor. 2. includes calibration tolerance, oper ating temperature, supply voltage variations, aging and ir re ow. 3. figure 3 de nes the test circuit and figure 4 de nes these parameters. 4. duty cycle is de ned as the on/time period. 5. measured using an agilent e5052. 6. measured using a lecroy wavemaster 8600a, 90k samples 7. measured using a wavecrest sia3300c, 90k samples. 8. outputs will be enabled if enable/disable is left open. t r t f v amp *0.8 v amp *0.2 cross point on time period v amp figure 2. 1 2 3 6 5 4 -1.3v nc nc v dd -1.3v 50
50
figure 1.
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com page3 performance speci cations 1. the vc-709 power supply pin should be ltered, eg, a 0.1 and 0.01uf capacitor. 2. includes calibration tolerance, oper ating temperature, supply voltage variations, aging and ir re ow. 3. figure 5 de nes these parameters and figure 4 de nes the test circuit. 4. duty cycle is de ned as the on/time period. 5. measured using an agilent e5052. 6. measured using a lecroy wavemaster 8600a, 90k samples. 7. measured using a wavecrest sia3300c, 90k samples. 8. outputs will be enabled if enable/disable is left open. table 2. electrical performance, lvds option parameter symbol min typical maximum units supply voltage 1 v dd 3.135 2.375 3.3 2.5 3.465 2.625 v v current (no load) i dd 60 ma frequency nominal frequency f n 13.5 170.000 mhz stability 2 (ordering option) 25, 50 or 100 ppm outputs output logic levels 3 output logic high output logic low v oh v ol 0.9 1.43 1.10 1.6 v v di erential output amplitude 250 350 450 mv di erential output error 50 mv o set voltage 1.125 1.25 1.375 v o set voltage error 50 mv output leakage current 10 ua output rise and fall time 3 t r /t f 400 ps load 100 ohms di erential duty cycle 4 45 55 % jitter, 156.250mhz 5 12khz - 50mhz 12khz - 20mhz 10khz - 1mhz j 200 150 100 fs fs fs period jitter 6 rms p/p cycle-cycle jitter 6 rms p/p random jitter 7 deterministic jitter 7 j 1.1 10.5 1.9 17.7 2.2 0 ps ps ps ps ps ps enable/disable output enabled 8 output disabled v ih v il 0.7*v dd 0.3*v dd v v disable time t d 200 ns enable/disable leakage current i e/d 200 ua start-up time t su 2ms operating temp. (ordering option) t op -10/70 or -40/85 c package size 5.0 x 7.0 x 1.6 mm dc 1 4 3 65 2 50 50 0.01 uf out out figure 3.
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com performance speci cations table 3. electrical performance, hcsl output parameter symbol min typical maximum units supply voltage 1 v dd 2.375 3.165 2.5 3.3 2.625 3.465 v v current (no load) i dd 30 ma frequency nominal frequency f n 13.5 170 mhz stability 2 (ordering options) 25, 50 or 100 ppm outputs output logic swing v oh 0.62 0.78 v output rise and fall time 3 t r /t f 400 ps load 50 ohms to ground duty cycle 4 45 55 % jitter (12 khz - 20 mhz ) 100.000mhz 5 j 300 fs period jitter 6 rms p/p cycle-cycle jitter 6 rms p/p random jitter 7 deterministic jitter 7 j 1.0 9.7 1.8 18.3 2.2 0 ps ps ps ps ps ps enable/disable output enabled 8 output disabled v ih v il 0.7*v dd 0.3*v dd v v disable time t d 200 ns enable/disable leakage current i e/d 200 ua start-up time t su 2ms operating temp. (ordering option) t op -10/70 or -40/85 c package size 5.0 x 7.0 x 1.6 mm t r t f v amp *0.8 v amp *0.2 cross point on time period figure 5. v amp 1. the vc-709 power supply pin should be ltered, e.g., a 0.1 and 0.01uf capacitor. 2. includes calibration tolerance, oper ating temperature, supply voltage variations, aging and ir re ow. 3. figure 1 de nes the test circuit and figure 2 de nes these parameters. 4. duty cycle is de ned as the on time/period. 5. measured using an agilent e5052. 6. measured using a lecroy wavemaster 8600a, 90k samples. 7. measured using a wavecrest sia3300c, 90k samples. 8. outputs will be enabled if the enable/disable pad is left open. page4 figure 4. 50 50 1 6 2 5 3 4
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com package and pinout table 4. pinout pin # symbol function 1 e/d or nc enable/disable 2 e/d or nc enable/disable 3 gnd electrical and lid ground 4f o output frequency 5cf o complementary output frequency 6v dd supply voltage figure 7. package outline drawing 7.00.15 5.00.15 1.40 1.10 3.7 2.54 5.08 frequency date code 1 3 1 bottom view 5 2 23 65 4 64 1.6 max figure 6. pad layout 1.96 3.66 5.08 2.54 1.78 hcsl application diagrams the vc-709 incorporates a standard high speed current logic, hcsl ,output scheme which is a 15ma current source switched betwe en out and comple- mentary out. being un-terminated drains, as shown in figure 8, they require external 50 ohm resistors to ground as shown in fi gure 9. hcsl is a high im- pedance output with quick switching times, in can be advantageous to use a 10 to 30 ohm series resistor as shown in figure 10, to help reduce overshoot/ ringing. figure 8. standard hcsl output con guration figure 9. single resistor termination scheme figure 10. in some cases a 10-30 ohm series resistor is used to help reduce overshoot. one of the most important considerations is terminating the output and complementary outputs equally. an unused output should n ot be left un-termi- nated, and if it one of the two outputs is left open it will result in excessive jitter on both. pc board layout must take this and 50 ohm impedance matching into account. load matching and power supply noise are the main contributors to jitter related problems. 15ma page5 50 50 1 6 2 5 3 4 z l =50 ohms z l =50 ohms 50 1 6 2 5 3 4 50 z l =50 ohms z l =50 ohms 10-30 10-30 dimensions are in mm
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com environmental and ir compliance table 5. environmental compliance parameter condition mechanical shock mil-std-883 method 2002 mechanical vibration mil-std-883 method 2007 temperature cycle mil-std-883 method 1010 solderability mil-std-883 method 2003 f i n e a n d g r o s s l e a k fine and gross leak mil-std-883 method 1014 resistance to solvents mil-std-202 method 215 m o i s t u r e s e n s i t i v i t y l e v e l moisture sensitivity level msl1 contact pads gold over nickel page6 lvpecl application diagrams lvds application diagrams the vc-709 incorporates a standard pecl output scheme, which are un-terminated fet drains. there are numerous application notes on terminating and interfacing pecl logic and the two most common methods are a single resistor to ground, figure 11, or for best 50 ohm matching a pull-up/pull-down scheme as shown in figure 12 should be used. ac coupling capacitor are optional, depending on the application and the input lo gic requirements of the next stage. 1 2 3 6 5 4 nc nc v dd 140
140
0.01uf 0.01uf 0.01uf figure 11. single resistor termination scheme resistor values are typically 140 ohms for 3.3v operation and 84 ohms for 2.5v operation. figure 12. pull-up pull down termination resistor values shown are typical for 3.3 v opertaion. for 2.5v operation, the resistor to ground is 62 ohms and the resistor to supply is 250 ohms one of the most important considerations is terminating the output and complementary outputs equally. an unused output should n ot be left un-termi- nated, and if it one of the two outputs is left open it will result in excessive jitter on both. pc board layout must take this and 50 ohm impedance matching into account. load matching and power supply noise are the main contributors to jitter related problems. 100
lvds driver lvds receiver 100
lvds driver receiver figure 13. lvds to lvds connection, internal 100ohm resistor some lvds structures have an internal 100 ohm resistor on the in- put and do not need additional components. ac blocking capacitors can be used if the dc levels are incompatible. figure 14. lvds to lvds connection some input structures may not have an internal 100 ohm resis- tor on the input and will need an external 100ohm resistor for impedance matching. also, the input may have an internal dc bias which may not be compatible with lvds levels, ac block- ing capacitors can be used. one of the most important considerations is terminating the output and complementary outputs equally. an unused output should n ot be left un-termi- nated, and if it one of the two outputs is left open it will result in excessive jitter on both. pc board layout must take this and 50 ohm impedance matching into account. load matching and power supply noise are the main contributors to jitter related problems.
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com table 6. re ow pro le parameter symbol value preheat time ts 200 sec max ramp up r up 3c/sec max time above 217c tl 150 sec max time to peak temperature tamb-p 480 sec max t i m e a t 2 6 0 c time at 260c tp 30 sec max time at 240c tp2 60 sec max r a m p d o w n ramp down r dn 6c/sec max suggested ir pro le devices are built using lead free epoxy and can be subjected to standard lead free ir re ow conditions shown in table 6. contact pads are gold over nickel and lower maximum temperatures can also be used, such as 220c. s ir compliance absolute maximum ratings and handling precautions stresses in excess of the absolute maximum ratings can permanently damage the device. functional operation is not implied or an y other excess of conditions represented in the operational sections of this data sheet. exposure to absolute maximum ratings for exten ded periods may adversely a ect device reliability. although esd protection circuitry has been designed into the vc-709, proper precautions should be taken when handling and mount ing, vi employs a human body model and charged device model for esd susceptibility testing and design evaluation. esd thresholds are dependent on the circuit parameters used to de ne the model. although no industry standard has been adopted for the cdm a standard resistance of 1.5kohms and capacitance of 100pf is widely used and therefor can be used for comparison purpo ses. s table 7. maximum ratings parameter unit storage temperature -55 to 125 c junction temperature 150 c supply voltage -0.5 to 5.0 v enable disable voltage -0.5 to v dd +0.5 v esd, human body model 1500 v esd, charged device model 1500 v maximum ratings, tape & reel table 8. tape and reel information tape dimensions (mm) reel dimensions (mm) w f do po p1 a b c d n w1 w2 #/reel 16 7.5 1.5 4 8 180 2 13 21 50 17 21 250 page7
vectron international ? 267 lowell road, hudson, nh 03051 ? tel: 1-88-vectron-1 ? http://www.vectron.com vc-709- pcie2 - 100m000000 product xo options supply =2.25-3.63v output = hcsl stability = 50 ppm over -40/85c enable/disable on pin 1 frequency in mhz package 5x7 page8 disclaimer vectron international reserves the right to make changes to the product(s) and or information contained herein without notice. no liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. rev: 03/28/2011 for additional information, please contact usa: vectron international 267 lowell road hudson, nh 03051 tel: 1.888.328.7661 fax: 1.888.329.8328 europe: vectron international landstrasse, d-74924 neckarbischofsheim, germany tel: +49 (0) 3328.4784.17 fax: +49 (0) 3328.4784.30 asia: vi shanghai 1589 century avenue, the 19th floor chamtime international financial center shanghai, china tel: 86.21.6081.2888 fax: 86.21.6163.3598 ordering information example: vc-709-ece-kaan-156m250 vc-709- e c e - k a a n - xxxmxxxxxx product xo voltage options e: +3.3 vdc 5% h: +2.5 vdc 5% output h: hcsl c: lvpecl d: lvds frequency in mhz *note: not all combination of options are available. other speci cations may be available upon request. temp range w: -10/70c e: -40/85c other (future use) n: standard stability f: 25ppm k: 50ppm s: 100ppm enable/disable pin a: pin 1 b: pin 2 package 5x7 enable/disable logic a: enable high pci express ordering information vc-709-107-frequency= lvpecl, +3.3v, 20ppm over -10/70c, e/d on pin1 vc-709-109-frequency= lvds, +3.3v, 20ppm over -10/70c, e/d on pin1 vc-709-110-frequency= lvpecl, +2.5v, 20ppm over -10/70c, e/d on pin1 vc-709-111-frequency= lvds, +2.5v, 20ppm over -10/70c, e/d on pin1 20ppm options
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